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Nano, Quantum and Molecular Computing
Implications to High Level Design and Validation
ISBN: 9788184893717
First Indian Reprint 2010 ,
376 pages, Soft Cover,
Rs. 795 /- For Sale in India, Pakistan, Nepal, Bangladesh & Sri lanka Only
Primary Audiences:
Students of Computer Science and Nano Technology

Computer Science and Nano Technology
gate failure probabilities, gate failure probability, clocking zone, nanoscale computation, clique energy, clocking level, defect tolerant architectures, logic block level, unbounded model checking, logic margins, restorative stages, nano architectures, thermal energy levels, reconfigurable fabrics, probabilistic model checking, nanoscale wires, quantum hits, majority gate, defect tolerance, electronic nanotechnology, carbon nanotube transistors, zone placement, kink energy, defect map, address wires. Law of Large Numbers, International Conference, Numbers System Design, Device Considerations, New York, Unreliable Nano Devices, San Jose, Computer Society Press, Cambridge University Press, Computer Aided Design, Custom Computing Machines, Design Automation Conference, Prentice Hall, Stanley Williams, Verification of Large Scale Nano Systems
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